The present invention pertains to the environment of a raster display system. Raster display device has been the main visual information presentation device in the information industry. It is defined here as a display device in which picture elements (pixel data) are presented to the screen in a fixed scanning order. The order can be repetition of left to right for a line and top to bottom for one screen or the other combinations as long as it is fixed in a particular system. Same scanning order can also happen in several sections of the screen alternatively or simultaneously. Thus the raster display device referred to in this invention includes CRT monitor and flat panels such as liquid crystal display (LCD), electroluminant display (ELD), and plasma display. Video controller designs for raster display system use either a synchronous or asynchronous clock for the three major functions--video memory control, video pixel processing, and video display control. Using a synchronous clock--that is, the same clock for the three major functions--the memory performance is limited and, in addition, design flexibility is significantly impaired.
Hence, to improve the designs, at least two asynchronous clocks have been used. In these types of systems, the video memory runs at a different frequency than the video processing circuit and display control circuit. In all previously known asynchronous video designs, the display control signals, for example, HSYNC, VSYNC, BLANK, DISPEN (DISPLAY ENABLE) and CURSON (TEXT CURSOR ON), are on the video clock side because they need to be synchronous to video pixel processing. Video pixel information is fetched from the video memory using memory clock. The problem with previously known asynchronous systems has been the need for the synchronization circuit between the memory control circuit and the display control circuit to coordinate the complex events happening in these two circuits running at different frequencies. This type of synchronization circuit is very complex and its functional reliability has been a main design problem in the prior asynchronous video architecture. What is required is a video controller design in which the limitation above described with synchronous systems such as memory performance and design flexibility are eliminated and, at the same time, the synchronization circuit design problems associated with such asynchronous systems are removed.